1. Field of the Invention:
The present invention relates to a semiconductor memory device, and more particularly to a memory device having a serial access port.
2. Description of the Related Art:
A serial access memory having a serial access port has been used as a video memory for storing image or video data. A dual-port memory is a representative example of the serial memory, which further has a random access port in addition to the serial access port. An example of the dual port memory is disclosed in U.S. Pat. specification No. 4,633,441 issued to Ishimoto. The conventional memory having the serial access port is constructed as follows. A plurality of memory cells are arranged in a matrix form of rows and columns and one row of memory cells are read out at a time in parallel. The serial access port has a data register for storing data read from the selected row of memory cells and a serial read circuit for serially reading data stored in the data register from an initial location one by one in synchronism with a shift pulse. The selection circuit includes a shift register whose output is used to select data to be read-out from the data register and a column decoder for controlling the shift register to determine the initial location in accordance with external column address information.
As the patterns have become finer and finer in semiconductor memories in recent years, defects of memory cells, word lines or bit lines tend to increase, and the necessity of using a redundancy circuit for replacing the defective memory cell, word line or bit line has arisen.
The conventional redundancy circuit of serial port includes a counter circuit receiving a first control signal for indicating an accessed address designated by the shift register, an address memory circuit for storing the defective address of a defective memory cell, bit line or the defective address of a serial register and a coincidence circuit for detecting coincidence between the output of the counter and the defective address and for outputting a second control signal for replacing the defective memory cell, bit line or serial register by the memory cell, bit line or serial register of the redundancy circuit.
In the serial memory having the redundancy circuit described above, setting of the initial address to the shift register and setting the counter at the time of data transfer are conducted simultaneously in accordance with the external address. Accordingly, the counter must be set at the initial state corresponding to the external address before the subsequent input of the first control signal and the count-up operation of the counter is performed by the subsequent input of the first control signal after the data transfer of read-out, data to the data register. When the time necessary for the shift operation of the shift register and the time necessary for the count-up operation of the counter are compared, the latter is generally longer. Therefore, there occurs the problem in that the period of the first control signal is elongated to make the operation of the counter synchronized with the operation of the shift register in the memory having the redundancy circuit. Therefore, the effective serial access speed performed by the shift register is lowered.